Energy-Efficient Ternary Multiplier

Multiplication is a fundamental arithmetic operation with applications in various fields, such as neural networks, signal and image processing. Ternary multiplication, an emerging area of research, explores the multiplication of numbers represented in the ternary numeral system. This paper proposes a new technique for computing partial product trits of multi-digit multiplication, along with improved adder modules, intending to reduce power dissipation. Two parallel paths have been proposed to calculate the final product, thereby improving the latency of the multiplier. The internal adder modules of the multiplier have been designed to optimise the number of transistors, resulting in lower power consumption. Results prove that the proposed design significantly improves power, delay, and the power-delay product (PDP). The proposed three-trit multiplier shows a 20.7% improvement in power, 23.17% in delay, 39.11% in PDP, and 18.76% in transistor count compared to the existing design.