Design and Implementation of Low Power Golay Encoder Architecture

In wireless communication, the transmission of a message from source to destination may be susceptible to distortion or corruption due to noise. Error detection involves identifying errors, while error correction entails restoring the original message. This work gives a through performance analysis of a Golay Encoder. To address these limitations of existing methods, a novel architecture has been introduced to generate the binary Golay code word of 23 bits output using the 12 bits input message signal using Clock gating technique. This new design emphasizes low power consumption, and it has been developed and confirmed through verification processes. Feedback shift registers based on linear (LFSR) cyclic redundancy check (CRC) and hardware architecture based on CRC [1]. These architectures do have some downsides. In order to reduce the power of Existing Method, we used the clock gating technology to reduce the power consumed by the clock signal. The main objective is to reduce the power consumption of the Existing Golay Encoder. As the major power consumption component is clock,we tried to reduce the usage of power by clock. The findings of this study aid in the selection and optimization of different clock gating technique. The results provided in this paper demonstrate the benefits of clock gating technique. This project is done uisng the Cadence 90nm technology. In this the total power of the system is reduced by 64.6%, the delay of the system is maintained constant and the area of the system is reduced by 2.7%.