Design and Analysis of FinFET Models Based Ternary 1-Trit Comparator

The advent of multivalue logics in the domain of digital electronics has been acknowledged as a noteworthy accomplishment, providing solutions to the limitations imposed by binary logic. Ternary logic is considered an innovative method within the field of multivalue logic. This article outlines the design of a ternary 1-trit comparator employing 18nm FinFET technology using the Virtuoso tool provided by Cadence. The analysis of the comparator's performance is conducted by comparing the outcomes acquired using SVT and HVT FinFET models. The simulation findings obtained indicate power consumption values as 29.24 and
$\mathbf{51.10}\boldsymbol{\mu}\mathbf{W}$
, transient delay values as 30.33 and 40.57ns, and power delay product values as 886.84 and 2073.12 (x 10
⁻¹⁵
J) for SVT and HVT FinFET models, respectively. The suggested architectural design of 1-trit ternary comparator proves to be energy efficient for applications where data sorting and decision-making is necessary.