Solving Mixed-Integer Optimization Problems in Microsecond Scale: A Scalable Real-Time Embedded Hardware Architecture

For the application of modern control and optimization techniques to power electronics applications, performing intensive computations on a microsecond-scale is of paramount importance. The optimization algorithms involved are in most of the cases NP-hard, involving integer variables and nonlinear objectives; their real-time implementation is done on embedded control platforms in the form of field-programmable gate arrays (FPGAs). These enable fast computation but also feature limited hardware resources that constrain the size of the problems that can be tackled. In this paper, we present a scalable digital hardware (HW) architecture implemented on an FPGA for the real-time implementation of a branch-and-bound algorithm for mixed-integer optimization. The need for such a solver stems from the concept of converter modulation, where an optimal voltage path of a certain length has to be reconstructed by the appropriate choice of a combination of integer variables. We showcase how the geometrical properties of the optimization problem can be exploited to enable a solution in microseconds, and how the FPGA design can be modularized to ensure that the HW resources are adequate even when considering longer voltage reconstruction paths which translate to an exponential increase in problem complexity.