Energy Efficient Electrolytic-Gated Synapse Transistors Using InGaZnO/HfO2 Gate Stacks With Vertical Channel Configurations

150-nm channel length vertical synapse transistor with oxide channel was demonstrated. The implementation of mesa-type vertical channels effectively minimized the device footprint, enhancing both the compactness and efficiency. The fabricated vertical synapse transistor exhibited a high on/off ratio of ${6}.{3}\times {10} ^{{10}}$ at a drain bias of 1 V and demonstrated a current drivability of $13.5~\mu $ A/ $\mu $ m. The superior on/off ratio ensures minimal leakage current, contributing to enhanced energy efficiency and serving as a strength in multi-levels implementations. In particular, the device has implemented the energy consumption at the fJ-level and 120 multi-levels, highlighting the strong potential of next-generation neuromorphic computing.