Constant-Time Synchronous Binary Counter with Minimal Clock Period

Many applications rely on synchronous binary counters because of their speed and support for a broad bit-width; these components are fundamental to very large scale integration (VLSI) architecture. When the counter size is not modest, most older counters have low counting rates due to their enormous fan-outs and extensive carry chains. This brief examines the smallest possible counting period for counter sizes varying from eight bits to one hundred and twenty-eight bits, and presents a novel, extremely fast structure for synchronous binary counting. A 1-bit Johnson counter, the most elementary unit, will be used initially. Minimizing the propagation latency caused by big fan-outs is possible by recreating the 1-bit counter. If the results of the experiment hold, the design can be implemented with a minimum number of flip-flops, the size of which is inversely connected to the size of the counter. It can only do as much as the least significant bit can count when using 65nm CMOS technology and a 2GHz clock frequency.