A Novel Resynchronization Circuit to Enable High-Accuracy PTP Timestamping

Precision time protocol (PTP) is widely used in network synchronization applications to achieve high-accuracy time and phase alignment that has become increasingly important in the era of 5G. This article discusses a method to improve hardware timestamping accuracy and, thus, enhance the time error (TE) performance in PTP systems. In many practical network systems, there is a need to have independent clock domains for PTP and for the Ethernet physical layer transceiver (PHY) system. The clock domain crossing of the time-of-day (ToD) timestamp values from the PTP domain to the PHY domain is a major source of TE. This work presents a design named fine-count lock loop (FLL) that can reduce the clock-domain-crossing error down to ±100 ps using an external phase measurement circuit. When integrated into a PTP system, the design achieved ±4.4-ns constant TE (cTE) and 4.74-ns filtered maximum absolute TE (Max $\vert $ TE $_{L}\vert $ ) to meet the International Telecommunication Union (ITU) Class D specification for PTP performance.