Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks

Advanced Encryption Standard’s (AES) vulnerabilities surfaced with Power Side Channel Attacks (PSCA). Enhancing security by adding extra countermeasure circuitry introduces significant hardware overheads, which are impractical for resource-constrained Internet of Things (IoT) edge devices. This study proposes an alternative approach, focusing on the AES design itself to enable lightweight countermeasures. Targeting the SubBytes round operation as the vulnerable point, the operation is split across different clock cycles to minimize side-channel information leakage. We investigated 12-clock, 22-clock, 42-clock, 82-clock, and 162-clock AES designs among which the 82-clock version stands out as the optimal choice, providing efficient hardware resource utilization. Evaluation using hardware security metrics, such as Measurements To Disclose (MTD) and Signal-to-Noise Ratio (SNR), confirms its superior security and reduced information leakage compared to other designs. Power traces for attacks are generated on both Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) platforms, maintaining a consistent 16 MHz design frequency with traces sampled at 1 GSa/s.