An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation

This article presents an injection-locked clock multiplier (ILCM) using a digitally controlled frequency-tracking loop (FTL) with an integral two-step switched-capacitor (SC) digital-to-analog converter (DAC). Conventionally, the DAC resolution needs to be increased for low noise at the cost of degraded monotonicity due to device mismatch. To overcome this tradeoff, the proposed DAC utilizes the SC technique to achieve fine steps. With only two capacitors involved in charge transfer, the DAC is inherently monotonic, avoiding the boundary-crossing issue and the mismatch calibration. A control-voltage-tracking loop (CVTL) further suppresses the quantization noise by balancing the up and down step sizes and helps achieve a 16-bit-level voltage step. The FTL is sub-sampling and utilizes a bang-bang phase detector (BBPD). Locking at 700 MHz, the ILCM achieves a 0.9-ps integrated jitter, a –125-dBc/Hz phase noise at a 1-MHz offset, and a small jitter variation of 2.67% under different supply voltages and temperatures. With FTL, the spur is around
$-$
56 dBc from the prototype fabricated in a 180-nm CMOS process. The chip occupies a core area of 0.054 mm
$^{2}$
and consumes 689
$\mu $
W from a 1.8-V supply, achieving an FoM of
$-$
242.5 dB.