Improved Fault Ride-Through Response of Grid Forming Inverters Under Symmetrical and Asymmetrical Faults

The voltage source behaviour of grid forming inverters is in demand owing to their instantaneous reaction to disturbances in the grid. However, this might lead to the flow of high magnitudes currents during faults. Thus advanced approaches are required which aid in successful fault ride-through (FRT) without hampering the current limits of the semiconductor switches. This paper proposes a virtual impedance based scheme to control steady state currents, while utilizing the direct modulation scheme of finite control set model predictive control (FCS-MPC) to limit the transient current peaks. The proposed approach limits inverter currents during both symmetrical and asymmetrical faults. The proposed grid forming control demonstrates high bandwidth in normal and sag voltage levels. Further the negative sequence current injection during an asymmetrical fault can also be controlled. Extensive simulations are performed on a grid connected network under variation of grid parameters. Further, the proposed method is applied to inverters operating in CIGRE low voltage benchmark networks which demonstrate successful FRT behaviour in grid connected and islanded mode. Experimental validation of the proposed approach is carried using controller-hardware-in-the loop setup with CIGRE network demonstrating the efficacy of the proposed controller even in back to back faults.