Suppression of Aliasing Errors Introduced by Non-Ideal Mixers and Spectrum Partitioning Methods in the FI-DAC System

With the growing demands for increased bandwidth in arbitrary waveform generator, the Frequency-Interleaved Digital to Analog Converter (FI-DAC) technology plays a crucial role in enhancing the output bandwidth of individual DAC chips. Based on a dual-DAC chip and band interleaving techniques, the research addresses the issue of aliasing errors resulting from the non-ideal performance of practical analog circuits. By modeling the aliasing errors in the system and the non-ideal characteristics of the hardware, the article aims to minimize aliasing errors while achieving maximum bandwidth output, in compliance with the sampling theorem. The process includes filter selection, determination of sub-band division points for two signal paths, and the system's maximum output bandwidth. Finally, the local oscillator frequency for the mixer is determined. In a simulated environment accounting for actual hardware error components, this study employs a 7th-order elliptic filter with 50 dB aliasing suppression. With two DAC chips operating at a 5 GSa/s sampling rate, the system achieves 3.992 GHz signal output. Under the constraint of employing two 5 GSa/s DACs, this method results in a 59.68% increase in output bandwidth compared to a single DAC output.