Deep Neural Network Representation for Explainable Machine Learning Algorithms: A Method for Hardware Acceleration

Deep Learning and Machine Learning algorithms achieved good results in various tasks, from computer vision and speech recognition to condition monitoring and predictive maintenance. Besides the good results obtained, most Deep Learning algorithms do not provide a precise interpretation of their decisions. For the purpose of interpretability, explainable ML has gained attention. Because hardware accelerators do not support most explainable Machine Learning algorithms, they frequently experience runtime deficiencies. The resulting need for comparably inefficient software implementations limits their use on edge-computing hardware. This paper presents a method to represent trained explainable ML algorithms as Deep Neural Networks to utilize hardware acceleration to meet the growing demand for accelerated inference of Machine Learning algorithms on edge hardware. The primary approach of the paper is to disassemble the trained explainable ML algorithms' inference into their basic mathematical operations to represent them as Deep Neural Network layers. The techniques to convert the trained model functionalities to Deep Neural Network layers are described in detail, including the layer functionalities and their usage in the Deep Neural Networks. Due to the wide use of Deep Neural Networks on hardware accelerators, this method allows the usage of affordable and efficient edge hardware instead of high-price, customized hardware and replaces the programming of high-effort compiler. Finally, the method is successfully applied to a part of an open-source ML toolbox, and the resulting Deep Neural network inferences are successfully run on a Neural Processing Unit.