LWECC: A Lightweight ECC Technology for HPC Accelerators Supporting Multi-granularity Memory Access

Heterogeneous multi-core accelerators have exhibited remarkable computational performance, establishing their competitiveness within the realm of high-performance computing. The on-chip memory to support reliable and correct data access is a crucial element of the accelerator. With the continuous scaling down of semiconductor process nodes, memory units become more susceptible to soft errors caused by Single Event Upset (SEU), thus significantly increasing the risk of memory access errors. Additionally, data interaction between cores supports a variety of granularities, making it challenging to achieve error tolerant designs for multi-granular data with low hardware overhead. This paper proposes the Light-Weight ECC (LWECC) integrated in the 64-bit accelerator’s Scalar Memory (SM) to improve the efficiency of data protection for multi-granularity memory access. LWECC adopts a software-hardware co-design approach, effectively balancing area overhead and providing comprehensive and flexible data protection. Compared to the finest-grained ECC solution as a baseline, using LWECC can reduce redundant memory area by 80.90% and ECC circuit area by 16.87%, markedly reducing the whole hardware overhead of the SM. In addition, LWECC efficiently caters to diverse application domains, supporting not only high-performance computing applications but also accommodating fine-grained memory access applications with low operational latency.