Design and Analysis of dual-k spacer CombFET for Digital and Synaptic Applications

This paper delves into the burgeoning realm of CombFETs, offering a comprehensive analysis of their structural design, simulation methodologies, and performance characteristics. With a focus on addressing the evolving demands of semiconductor technology, particularly in the sub-5-nanometer nodes. This study explores the efficacy of CombFETs as viable successors to conventional transistor architectures. Through detailed simulations, key geometric parameters such as interbridge width (W_IB) and height (H_IB) are investigated, revealing their profound impact on device performance metrics. Around 89.79% increment in average power and a 1.805× increase in switching current (ISC) is noticed when H_IB is varied from 10 nm to 30 nm for Nand gate. Moreover, CombFET based LIF neuron is designed and performance is analyzed at different values of HIB. Circuit-level analyses further demonstrate the compatibility and effectiveness of CombFETs in practical electronic systems, showcasing their potential for driving advancements in computing and neuromorphic architectures. This study underscores the pivotal role of CombFETs in pushing the boundaries of semiconductor technology, offering insights into their optimization and integration into nextgeneration electronic devices.