A Detailed Analytical Switching Transient Model for Silicon Superjunction MOSFET and SiC Schottky Diode Pair

With high reliability and good cost-performance ratio, silicon superjunction mosfets (Si SJMOS) and SiC SBD pair is often preferred in commercial single-phase power factor correction applications. Switching dynamics of Si SJMOS are different compared to 650$\,$V wide bandgap devices due to differences in device characteristics. This article presents an improved analytical model to study the switching dynamics of Si SJMOS and SiC SBD pair. Unlike the existing literature on high-voltage Si mosfets, this article considers the nonlinearities in channel current and internal capacitances of Si SJMOS, the nonlinear reverse-biased capacitance of SiC SBD, along with parasitic gate-drain capacitance arising due to PCB layout. As a result, the proposed analytical model presents a significant improvement over the existing models of high-voltage Si mosfet in predicting switching loss, time, $(dv/dt$), $(di/dt)$, etc. Experimental and simulation results for three 650 V Si SJMOS and SiC SBD pairs with different current ratings provide validation of the proposed analytical model.