Design and implementation of FPGA-based hardware acceleration for Machine Learning using OpenCL: A case study on the K-Means algorithm

The complexity of data analytics applications has led to an exponential increase in demand for effective and high-performance data clustering solutions in recent years. This paper presents a technique for optimizing the speed of the widely-used K-means clustering algorithm, utilizing Field-Programmable Gate Arrays (FPGAs) and High-Level Synthesis (HLS). By taking advantage of FPGAs' parallel processing capabilities, a methodology built on the Open Computing Language (OpenCL) was presented, which significantly improved algorithmic efficiency and addressed the computational bottlenecks encountered in large-scale data clustering applications. We present a detailed overview of the OpenCL framework integration and the FPGA- based hardware acceleration framework for K-means algorithm optimization. Furthermore, this implementation can be fully realized without the need for Hardware Description Language (HDL) code. The performance improvements obtained using OpenCL-based FPGA acceleration are demonstrated through experimental evaluations on randomly generated float datasets, which demonstrate notable speedups over conventional software implementations. Experimental results demonstrate that FPGA- based accelerators offer significantly improved execution times, ranging from 3 to 16.7 times faster compared to traditional CPU implementations.