Integrated Circuit to Compensate Parasitic Leakage Component for WL Leakage Current in nand Flash Memory

In this letter, we propose a new method to independently detect leakage current in the main cell area by eliminating parasitic components in the peripheral circuit area that can impact defect detection accuracy. In addition, Gm mismatch calibration technology is introduced to enhance the accuracy of the defect detection circuit. Word line defects that occurred at a level of 4000 ppm after screening with the conventional method were reduced to 0 ppm after screening with the new method, resulting in zero defects.