Design of Flash ADC with CMOS Logic Using 45nm Technology

This paper presents the design of a Flash analog-to-digital converter (ADC) with 5-bit resolution using complemen-tary metal-oxide semiconductor (CMOS) logic with 45nm tech-nology. The methodology comprises of resistive ladder network, thermometer code generation, binary encoder, and comparator. A two-stage operational amplifier functions as a comparator, which generates the thermometer code, and the priority encoder translates this code into binary output. The resultant binary output is the digital output of the Flash ADC. The primary issue in the Flash ADCs was frequently stems, hence the area and circuit power consumption increases with the increase in resolution bits. The main goal is to optimize the encoder circuit that enhances the bit count and reduce ADC power consumption. To reduce power consumption, the encoder is built using a 2:1 multiplexer based on several logics such as transmission gate logic, pass transistor logic, and CMOS logic. The results shows improvement in resolution and reduced power consumption.