SSTL IO Standard Based Low Power Design of DES Encryption Algorithm on 28 nm FPGA

The principal objective of the Input Output (IO) standard is to match the impedance of the info and result port alongside FPGA gadget. During our exploration, we saw that different IO guidelines are taking various powers however the usefulness of safety. The calculation is something similar with various IO Norms. In this work of hardware security, we are utilizing various Stub Series Terminated Logic (SSTL) IO Standards accessible on 7-Series FPGA. We have taken the HDL Code of the DES Calculation and executed on 7-Series FPGA. The calculations have an enhanced power utilization with SSTL 135 IO standard.