Carry Select Adder Using Square Root Techniques in Ripple Carry and BCD Adders

Carry select adder (CSA) finds application in increasing the speed of additions in various processing units. However, the design of this CSA is a challenge because the gates used in it and their complexity, delay in propagation of output bits decide the efficiency of the designed CSA. In this paper, a CSA with square root technique which includes BCD adder, ripple carry adder, mux with various dimensions and basic full adders are used. Further, it is extended with 1-bit binary to excess conversion for improving the CSA performance. Xilinx Verilog is used for the performance analysis of various CSA architectures.