Design of a Power-Efficient Static Random Access Memory Cell with Enhanced Stability for Internet of Things Applications

In today's tech-driven era, where the need for swift data processing is paramount, memory emerges as a critical component, playing a key role in ensuring the high speed functionality of modern devices across diverse applications. From IoT devices and embedded systems to networking applications, SRAM (static random access memory) plays a pivotal role across a multitude of domains, illustrating its versatile and widespread use in diverse technological fields. In all these domains, high-speed processing is essential, underscoring the critical need for efficiently storing and swiftly accessing digital information. In this work, a bit-line enabled IT SRAM cell (BLE10T), designed for low power consumption is presented, that also shows improved access time and Static Noise Margin (SNM). The efficacy of low power BLE10T SRAM cell is also compared with conventional 6T SRAM cell. Comparing the BLE10T SRAM cell with the conventional 6T SRAM cell shows that the low power BLE10T SRAM cell consumes
$\boldsymbol{1.52}\times, \boldsymbol{1.05}\times$
and
$\boldsymbol{2.35}\times$
times less power during hold, read and write operation. Moreover, it is
$\boldsymbol{1.67}\times$
times faster during read operation and
$\boldsymbol{1.15}\times$
times faster during write operation. The static noise margin during hold, read and write operation is improved by
$\boldsymbol{1.01}\times \boldsymbol{1.94}\times$
and
$\boldsymbol{1.05}\times$
respectively, compared to conventional 6T bit-cell. The BLE10T cell and conventional 6T cell are simulated at 45nm technology node using cadence virtuoso simulator.