Area And Speed-Efficient Vedic RISC Processors for Embedded Systems

This paper provides the architecture for high -speed multiplication using one of the Vedic arithmetic approaches. This strategy is used to increase speed. The compressor-based multiplier outperforms other stranded techniques like array and booth in terms of speed and space. Efficient multiplication is critical in computer design, particularly in DSPs where signal processing is a primary responsibility. The CPU is compact and efficient, making it suitable for usage in small-scale embedded systems or IoT nodes. The Vedic Arithmetic and Logical Unit (ALU) refers to the use of Vedic mathematical ideas for arithmetic operations. This option may aid in making mathematical computations faster and more efficient. For simulation, the Xilinx ISE tool is used, which is often used for FPGA design. This procedure facilitates the verification of the design's functionality and performance before actual hardware implementation. Because of their flexibility and reconfigurability, FPGAs are perfect for prototyping and deploying customized CPUs.