Design of Recursive Decoding based Coupled Turbo Encoder-Decoder for VLSI Applications

Designing error detection and correction codes for System on Chip (SoC) presents a significant challenge in VLSI design, mainly due to the inherent limitations in computation power and memory often associated with SOCs. Turbo codes, a specific class of error detection and correction codes, pose a viable solution with their moderate complexity, despite exhibiting a sharp increase in the error floor. The term "turbo" is aptly chosen as two decoders work in tandem to simultaneously decode the encoded bit sequence, resembling the collaborative action of turbo engines. This approach allows for the efficient handling of the extensive data processing demands inherent in the encoding process. In an attempt to produce a code that would produce even less error in the waterfall area of the BER than the already efficient turbo codes, several earlier methods have attempted to link the information bits in the code blocks. To improve upon the performance of the only information linked or partially coupled turbo coding approach, the suggested technique proposes to couple the adjacent code block information and parity bits. The error rate with respect to iterations to convergence is used to assess the suggested system's performance. Bits in only adjacent blocks are combined to minimize hardware complexity as well as reducing connecting wire lengths in multi layer PCBs which may result in electromagnetic interference. A comparative analysis with existing benchmark models in the domain clearly indicates the superior performance of the proposed approach compared to existing research in the domain.