Yield Improvement in 4X Node Technology ETOX NOR Flash by Optimizing Control Gate Related Process and Design

The cause of 4Xnm NOR-flash low yield and corresponding optimized manufactural process have been investigated in this paper. Some stack poly gate etching recipe splits are done to solve word line bridge formation mechanism. To solve word line bridges problem, we can increase control gate recipe organic bottom anti-reflective coating over etching time. After the process optimization, the control gate poly residues are eliminated and the chip prober yield rate is greatly improved. In addition, a novel design of inserting dummy active area under the control gate ends is proposed to eliminate the word line bridge.