Feasibility Analysis of Skip ILD CMP Scheme on 28nm Technology Node

Scratches from ILD CMP (Inter-layer Dielectric Chemical Mechanical Planarization) process directly affect the yield and reliability of devices, which is increasingly serious as the design rule shrinks. Out of the purpose of cost-reduction and yield-improvement, we propose a novel scheme of skipping ILD CMP on 28nm technology node. In this work, feasibility of Skip ILD CMP scheme has been verified by ADI (After Development Inspection) data, AEI (After Etch Inspection) data, oxide profiles, defects. The experimental results showed the acceptable variation of CD and CDU after lithography and etch, both excellent local and global planarization of oxide surfaces were achieved by CTW CMP, and the scratches were effectively avoided.