A 16MHz CMOS RC Frequency Reference with ±125ppm Inaccuracy from -40°C to 85°C Enabled by a Capacitively Modulated RC Time Constant (CMT) Generation and a Die-to-Die Error Removal (DDER) Technique

Monolithic RC frequency references offer attractive integration, cost, and power benefits compared to bulky crystal or MEMS oscillators. However, while the temperature coefficients (TCs) of on-chip MIM capacitors is small (tens of on-chip resistors have large TCs (up to thousands of and process variation, that ultimately limit performance. For a stable RC time constant $(\tau_{\mathrm{R}\mathrm{C}})$, CMOS RC frequency references usually require delicate design techniques to compensate for the TC and process spread of the on-chip resistors, commonly implemented by manipulating resistors of different TCs or using high-order polynomial compensation [1]–[3]. Fig. 1 (top-left) shows a conventional practice of TC calibration for $\tau_{\mathrm{R}\mathrm{C}}$, where a second resistor $\mathrm{R}_{\text{Trim}}$ with a different TC profile is used to cancel or adjust the first-order TC of $\mathrm{R}_\tau$. Due to the high-order TCs of both $\mathrm{R}_{\text{Trim}}$ and $\mathrm{R}_{\tau}$, the TC of $\tau_{\mathrm{R}\mathrm{C}}$ is still high after such calibration. As a result, high-order batch trimming based on polynomial compensation up to $6^{\mathrm{t}\mathrm{h}}$ order is used to reduce the TC of [4]–[6] as shown in Fig. 1 (top-right). However, the residual die-to-die error (DDE) due to process spread after such batch trimming limits the TC to ±200ppm or more [4], while a TC of ±90ppm is achieved at the cost of a compromised supply sensitivity and an increased power overhead [5].