A Novel CMOS High Frequency Frequency Divider

We propose in this paper an ultra high speed buffer-latch divider. The use of a single buffer instead of a D-latch reduces the equivalent capacitance, and hence increases the speed of the divider. The free-running divider frequency is almost twice as that of the conventional DFF divider. Moreover, the new divider consumes almost the same power as the conventional one, realizing a good compromise between power and speed. Analytical expressions of the locking range, amplitude, and frequency are given, and validated using simulations.