A High-Speed 64-kbit CMOS RAM

The first memory of a high-performance CMOS 64K family, an 8K X 8 asynchronous static RAM, has been developed using a full CMOS six-transistor memory cell approach to reduce power consumption and enhance endurance in disturbed environments. New design techniques have been adopted to optimize both speed and power dissipation. Built on a self-aligned CMOS technology with 1.5-/spl mu/m design rules, the circuit reaches the size of 45 mm/sup 2/ and achieves access times of 35 ns under typical conditions. To improve fabrication yield of the memory, redundancy assistance has been utilized allowing correction of physical defects by column replacement.