A GaAs 16x16 bit parallel multiplier

A GaAs 16/spl times/16-bit parallel multiplier has been constructed using a direct-coupled FET logic (DCFL) circuit with tungsten silicide gate self-aligned technology. This circuit chip, containing 3168 NOR gates with 2-/spl mu/m gate length enhancement/depletion FETs, is the most complex GaAs integrated circuit reported to date. MESFETs with the gate finger oriented in the [011] direction, which showed a smaller threshold voltage deviation, were used to realize this 3000-gate LSI. This multiplier has a multiply time of 10.5 ns, with a power dissipation of 952 mW at a supply voltage of 1.6 V. The projected performance, assuming 1-/spl mu/m gate length, is a multiply time of 6.5 ns.