Architecture Derivation for FPGA‐based DSP Systems

Abstract

This chapter explores the direct mapping of simple digital signal processing (DSP) systems or, more precisely, DSP components such as FIR or IIR filters and adaptive filters, as these will now form part of more complex systems such as beamformers and echo cancelers. The key aim is to investigate how changes applied to SFG representations can impact the FPGA realizations of such functions. The chapter focuses on demonstrating how the designer can start to explore the trade‐offs in an algorithmic representation, by starting with an SFG or DFG description and then carrying out manipulations with the aim of achieving improved performance. Given that a key aspect of FPGA architecture is distributed memory, efficient pipelining is a key optimization and so is explored in detail. The chapter then explores how the levels of parallelism can be adjusted in the implementation in order to achieve the necessary speed at both lower or higher area costs.