Gate‐All‐Around (GAA) Nanowire for Vertical Memory

Summary

This chapter describes the development of gate‐all‐around (GAA) cylindrical nanowire (NW) vertical 3D memory. Early development in vertical GAA charge‐trapping (CT) memory with single‐crystal silicon nanowires is explored along with physical characteristics of these memories. Nanowire memories were made from SOI silicon fins and from bulk substrates. High‐κ dielectrics and metal gate were used in single‐crystal silicon GAA NW CT memory to improve memory characteristics. Process development and characteristics of GAA CT memory with polysilicon NW were determined. Characteristics of junctionless polysilicon GAA NW memory were explored along with simulation and modeling. Both horizontal stacked NW memory and vertical pipe 3D NW memory were developed using single‐crystal NWs and using polysilicon NWs. Multiple SiGe/Si epitaxial layers were used to form stacked horizontal NW memory. An electrical layer selection method and array operation for stacked horizontal GAA NW memory arrays were described. Process technologies for vertical pipe GAA CT memory and memory characteristics were developed. NW memory with graphene channel is mentioned and a cost analysis of 3D vertical memory is described.