3D Memory Using Double‐Gate, Folded, TFT, and Stacked Crystal Silicon

Summary

The FinFET flash was an early vertical memory and could be made on both SOI and bulk substrates. These double‐gate or tri‐gate structures eliminated short‐channel effects and subsurface leakage as well as increasing channel length and ON current. Coupling ratio could be improved by high‐κ interpoly dielectric (IPD). Twin FinFET flash was made by dividing the fin, which doubled the bit density. Long FinFET NAND flash strings were demonstrated. Vertical channel double‐gate flash cells were developed using silicon fins. Double‐gate dopant‐segregated Schottky barrier (DSSB) charge‐trapping (CT) FinFET flash was studied. A double‐gate thin‐film transistor (TFT) CT flash memory string was discussed along with a double‐gate polysilicon nanowire (NW) flash memory. TFT CT flash memory was developed. Graphene channel CT memory was discussed. Double‐gate vertical single‐crystal silicon channel flash memory was developed with a bandgap‐engineered CT SONOS (BE‐SONOS) tunnel layer. Vertical gate TFT NAND strings were stacked in multiple layers using junctionless buried channel CT devices. An eight‐layer 3D vertical double‐gate TFT NAND flash with junctionless buried channel was developed. Stacked crystalline silicon epitaxial layers with planar memory arrays in each layer were developed. 6T SRAMs with double stacked (S³) transistor cells and double stacked NAND flash chains were made on these single‐crystal layers.