Test patterns for EPROMs

Detectable failure modes are clarified for each writing pattern. The write and erase modes for EPROM are expressed by six matrices. Four matrices express the failure modes in address, decoder and data input/output circuits, one expresses the write pattern and the last expresses bad bits in the memory array. Using this matrix method, it is clarified that the undetectable failure mode number in a 3/spl times/3 memory array is zero with a write pattern which is not a checker pattern. In addition, the failure detection rate in all `1' patterns is calculated to be about 30 percent (MNL=5) in the case of a 1 kbit memory array.