I/sup 2/L and high-voltage analog circuitry on the same chip: a comparison between various combination processes

Comparative experiments are presented for the I/SUP 2/L properties of: method (a) a standard 25 V BV/SUB CE/ analogue process; method (b) a modification of the same process with an extra N/SUP +/ diffusion giving deeper I/SUP 2/L collectors; method (c) a modification giving a more shallow I/SUP 2/L base; and method (d) two modifications involving a selective doping of the epi layer in the I/SUP 2/L part. Aside from the additional step in each method all process parameters, as well as the I/SUP 2/L gate geometry are kept the same. It is found that processes (d) give significantly higher effective gain for the n-p-n switching transistor than the other methods. The optimum speed is also higher for these processes, but the other methods have a lower power-delay product at low current level. THe reasons for the differences are analyzed. For one of the processes (d) the effect of a shallow versus deep N/SUP +/ guard ring is discussed, and the sensitivity to variations in process parameters is commented on.