A charge-pumping-loop concept for static MOS/RAM cells

A novel bistability concept based on a charge-pumping loop is presented. The loop consists of a charge pump and a simple two-device inverter. With an additional select transistor, the loop can be used as a static MOS/RAM cell. The proposed cell configurations are realized with only four devices, one or two shared supply lines, and an address-bit line pair. Feedback is accomplished with a single non-cross-coupled path. These cells can be manufactured with any industry-standard technology in a considerably smaller silicon area in comparison with the conventional flip-flop configuration. The standby power-dissipation level of the cells is also sufficiently low to meet the objectives of the high-density RAM design.