Design and Analysis of Low Power and High-Speed Baugh Wooley Multiplier using Modified Gate Diffusion Input Technique

An approach for carrying out signed binary multiplication is the Baugh Wooley Multiplier. By using this, positive and negative numbers are implemented with efficiency. In order to obtain the desired outcome, fewer partial products must be introduced. When compared to other multipliers, the Baugh Wooley multiplier requires fewer hardware resources to build since it employs fewer gates and adders in its design. This results in the multiplier being more efficient. Microcontrollers, digital filters, DSP processors, and other applications all employ the Baugh Wooley multiplier. Using three distinct methods—CMOS, GDI, and MGDI—this Baugh Wooley multiplier is implemented. The majority of integrated circuits employ the Complementary Metal Oxide Semiconductor (CMOS) technology, which uses more transistors and requires higher power dissipation and delays. The proposed multiplier has been designed and implemented in Custom Compiler of Synopsys at 32nm technology.