Key aspects in the development of a 48-channel duobinary PCM repeater

Discusses the development of the 48-channel modified duobinary PCM line repeater and the reasons for the choice of the modified duobinary coding technique. The hardware implementations of the various repeater sections-equalization, clock recovery, and data regeneration-are outlined, and the main considerations in circuit design, which are of prime importance for the modified duobinary system to retrofit the existing T1 system are described.