Digital to Pulse Converter for Analog in Memory Compute Applications

This work presents a novel approach in Digital to Pulse Converter (DPC) design, which is used as an alternative to Digital to Analog Converter (DAC) for Analog in Memory Compute (AiMC) applications. The proposed design utilizes a single Delay Locked Loop (DLL) to generate phases locked at 100 ps delay, which are then fed to multiple Pulse Width Modulators (PWM) needed in the chip. The system operates at an input clock of 200 MHz and the power consumption is simulated to be 5.70
$\mu \mathrm{W}$
for the PWM Encoder and 250.89
$\mu \mathrm{W}$
for the DLL. The circuit is designed in 22FDX™ technology. The area efficient PWM Encoder has a size of 35.20
$\times 1.04\mu{\mathrm{m}}^{2}$
. The area of the DLL is 38.24
$\times 16.60 \mu\mathrm{m}^{2}$
.