Double Gate JLT Based New TIGFET for Dynamic C2MOS Application

A sequential element can either be built by static logic or dynamic logic where the later is employed to achieve higher performance. However, the synchronous dynamic design using clocked CMOS (C²MOS) is mainly affected by reliability issues along with the problem of charge sharing by internal nodes. Such logic style can be revived if internal node count is optimized and Three Independent Gate FET (TIGFET) has potential in this regard. Hence, this article unveils a new 14nm Triple Independent Gate Junctionless Transistor (TIGJLT) based on double gate junctionless transistor (DGJLT) configuration. The 2D simulation of the proposed TIGJLT is carried out on Sentaurus TCAD to analyze metrics like subthreshold slope (SS), transconductance (GM), threshold voltage (V$T$H) and ION/IO F F ratio as a function of biasing at control gate and polarity gates. The mixed-mode simulation of C²MOS latch using the new device provides significantly lesser delay than the conventional counterpart due to the internal node elimination. Further, this TIGJLT offers dual V $T$ H that gives more flexibility to tune the leakage, power and speed of various VLSI circuits.