Dynamics of Domains and Its Impact on Gate Tunneling in CMOS-Compatible FeFETs

The ferroelectric layer thickness in the CMOS-compatible FETs must be scaled down to the nm dimension. At such thicknesses, direct gate tunneling becomes a prominent consideration for device scaling. We utilize phase-field simulation (2-D electrostatics with ferroelectric’s thermodynamic state model: depolarizing energy + gradient energy + free energy) to analyze the impact of multi-domain density on the gate tunneling in a FeFET. We observe that the transmission probability of the electrons (channel to the gate) is the highest in the domain wall region, which significantly depends on the spatial gradient in the domain’s polarization. Notably, a broader domain wall causes a gentle variation of the domain’s polarization, reducing the gate tunneling current than a hard domain wall. Furthermore, the drain electric field induces domain wall nucleation and a change in the position of domain walls, drastically altering the transmission probability. The device design guidelines are obtained by considering both the gate direct tunneling current and the memory window, which can be used to choose the desired ferroelectric/dielectric thicknesses for optimum performance.