TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection

The devices fabricated with the latest sub-nanometer technology node have a higher probability of parametric and wear-out failures, operational faults, and manufacturing defects, and these devices are more susceptible to intrinsic and extrinsic noise, resulting in soft errors. The parts with manufacturing defects are generally screened out during end-of-manufacturing tests. Thus, the soft errors during normal operations are of great concern. The soft errors in GPGPUs result into silent data corruption and control flow divergence errors. In order to deal with this, dual and triple modular redundancy architectures are used for soft error detection and correction, which result in large areas and power overheads. To overcome this, we propose a low overhead fault-tolerant microarchitecture called Trace Consistency Check (TCC) to detect the decoder and control flow divergence errors. The TCC is transparent to the application software. For error detection, we exploit the execution model of GPGPUs, where the warps of kernel executing in the streaming multiprocessor have temporal execution repetition. Hence, the instruction execution trace and control divergence paths across the warps are consistent. Inconsistency across warps for the same code region is attributed to decoder or control divergence errors. For error detection, new microarchitecture structures called Execution Trace buffer and Control Divergence Trace buffer were introduced to store and check the trace consistency across warps. The performance of TCC is evaluated through the ISPASS 2009 and RODINIA benchmarks. TCC's error detection capability and power overheads are evaluated. The simulation results show that TCC detects greater than 99% decoder and control flow errors with low power and no performance overheads.