Low-threshold low-power CMOS/SOS for high-frequency counter applications

A deep-depletion-process technology is described for the fabrication of complementary metal-oxide semiconductor integrated circuits on thin silicon films on sapphire. The process yields transistors which contain p/SUP +/-doped polysilicon self-aligned gates on a single n-silicon epi layer. Threshold dependence on carrier concentration and film thickness is analysed as well as device leakage currents. It is shown that n- and p-channel transistors can be fabricated with thresholds below +0.5 V and -0.5 V, respectively. The technology is applied to a 22-stage counter suitable for watch-circuit applications, and the average current as a function of applied voltage and operating frequency is analysed. Data are presented showing the performance of the counter when driven with a pulse generator and also with a crystal oscillator. It is seen that the circuit will operate at frequencies above 4 MHz with 1.4 V applied to the circuit and draw a total average current of less than 10 /spl mu/A.