A surface-charge correlator

Surface-charge transfer techniques have been used to implement a cross-correlator module in which the tap weights are restricted to values of plus and minus one. This compromise permits most of the advantages of CTD's to be retained, and the disadvantage of fixed tap weights can be overcome by using a weighted binary code for the tap weight function and separate binary correlators for each binary digit. A new architecture (parallel transfer) was used which eliminates the cumulative effect of charge-transfer inefficiency, thereby permitting longer impulse responses to be implemented than is practical with the conventional series transfer approach. The experimental device, which contains 32 stages, was implemented in p-channel MOS technology, and was designed to operate at 4 MHz. Test results are presented showing that a tap weight accuracy of order 1/2 percent can be achieved on a single chip. Presuming that the modular approach employed permits selection of well-matched chips with leakage at least as low as was obtained in the experimental units, it would be possible to implement an impulse response covering 40000 samples with tap weight accuracy of perhaps 1 percent.