Ultra Low-Power Implementation of PTL based 1 -Bit Full Adder Using CNTFET Technology

In this study, a 1-bit Full Adder (FA) is implemented by utilizing 2:1 MUX based on Pass Transistor Logic (PTL) structure using Carbon Nano Tube Field Effect Transistor (CNTFET) Technology. Then, the implemented circuit is compared with existing full adder circuits like FA using Complementary pass transistor (CPL), FA using Transmission Logic (TGL), FA using PTL and FA using CMOS. The parameters based upon which circuits are compared are Delay, Power and Power Delay Product (PDP). Simulation is done with help of HSPICE tool at 16nm technology node. After simulation, the results showed that least PDP is shown by FA designed using CNTFET technology with value of 0.0876 (aJ) as compared to existing full adders. This proves that CNTFET technology is an emerging technology and can be used in place of other technologies for designing of low power digital circuits.