A Novel 0.04 pJ/bit Dynamic TRNG using Bit Reconfigurable Ring Oscillators

True Random Number Generators (TRNGs) form the core and foundation of secure systems, ensuring the consistency and integrity of cryptographic operations. Their robustness and reliability significantly contribute to safeguarding sensitive information against potential threats and breaches. TRNGs rely on natural fluctuations, sourcing noise from various unpredictable physical phenomena, including thermal, electronic, and quantum effects, to generate high-entropy signals. While analog TRNGs offer effective solutions, an all-digital, CMOS-manufacturable approach is highly desir-able for several reasons: (1) low-power consumption, (2) cost-effectiveness, and (3) dependability. This proposed design is one such attempt, presenting a flexible framework that dynamically selects among several unique Ring Oscil-lators (ROs) to generate truly random bits. Remarkably, it achieves a random-number generation rate of 1 Gbits/sec while consuming only 1 pico.loule (pJ) every 25 random bits generated and has a Gate Equivalence (GE) of only 119. These findings were validated in Cadence's Virtuoso and Design Vision software environments, respectively. As a low-power design, its average power consumption was a mere 34.12μW. Additionally, it underwent synthesis on an Altera Cyclone V FPGA, successfully passing all the NIST SP800 test suite for randomness. This validation substan-tiates its effectiveness in a real hardware implementation, making it applicable across various decentralized domains such as Edge Computing, Internet of Things, and Federated Learning.