A 40-ns 144-bit n-channel MOS-LSI memory

The analysis and characterization of a MOS random-access memory is described. An optimization technique is developed that minimizes cycle time by selection of the optimum cell dimensions for a prescribed fabrication technology. These considerations are applied to the design of a high-speed 144-bit MOS-LSI memory using n-channel devices. This memory operates with a WRITE cycle of 40-ns, which is somewhat greater than the predicted value due to the nonideal drive pulse waveform.