Improving Clock Frequencies in ASIC Designs through Semi-Automatic Register Placement and Advanced Retiming

In hardware design, pipelining is a key technique for achieving high clock frequencies, typically by placing registers along the critical path of a design to minimize its length. As the complexity of hardware designs has increased, the potential for deeper pipeline configurations has emerged. Modern synthesis tools utilize register retiming, which adjusts register locations to balance the critical paths between them. Designers have several choices when tackling such challenging designs: place registers at the end of the design in conjunction with the synthesis tool’s retiming, optimize register placement manually to balance path distances, or combine both strategies. The pursuit of peak clock frequencies often requires the labor-intensive manual approach.In this paper, we present an innovative method that semi- automatically places registers along a design’s critical path as an initial seed that is subsequently used for retiming. Our case study, which analyzes several state-of-the-art regular and irregular multiplier designs synthesised for an ASIC technology for challenging environments, shows that this enhanced retiming increases the maximum achievable clock frequencies by up to 51 % over the traditional register appending method. Compared to the manual approach, the performance is similar, but the manual effort is greatly reduced.