Optimization analysis of high-speed differential signal vias in package

As the operating frequency of high-speed signals in the package continues to increase, the rise time of signal continues to shorten, resulting in an increasingly significant impact on signal quality. In particular, for via structures of the large-size and high-multilayer substrate in the integrated circuit (IC) package, as the frequency increases and the rise time shortens, the via holes impedance is discontinuous, and parasitic capacitance and inductance can cause signal reflection and attenuation, leading to signal integrity problems. In this study, the three-dimensional modeling of differential vias, and the parameterization of its model data are performed by HFSS software. According to the different design requirements in the early stage of IC package design, the differential vias center distance, via, pads , and anti-pads are quickly parametrically swept to simulate the TDR impedance and S-parameters under different variables. Further optimize the via structure by analyzing the signal integrity problem caused by the via structure providing support and guidance for the subsequent packaging design.