Embedded Wafer-level Microfluidic Cooling Designs for The System on Wafer Packaging

In the post-Moore era, System-on-Wafer (SoW) has been proposed to overcome the intractable advanced process nodes issues faced by Systems-on-Chip (SoC). SoW primarily relies on advanced packaging technologies such as 2.5D, 3D, and fan-out packagings that must be cost-effective and reliable. Consequently, the cooling or thermal management issues are especially challenging since SoW concentrates the thermal power onto the wafer scale.Here, this paper proposes a high-efficient and flexible embedded liquid cooling solution for the thermal management of a 4-inch SoW. The following structures by directly etching micrometer-sized channels in the backside of a wafer were considered: serpentine, parallel, spiral, and six-quadrant microchannel networks with straight-line shapes at a depth of 100 μm. The thermal resistance, pumping power, average heat transfer coefficient, and cooling coefficient of performance of different microchannel heat sinks (MCHS) were evaluated with a constant volumetric flow rate of cooling water. The simulation results revealed that for a 4-inch SoW with a heat flux of 13 W/cm² and a water flow rate of 0.12 L/min, the serpentine microchannel enabled the smallest temperature rise due to the highest effective heat transfer coefficient. However, the six-quadrant microchannel facilitated the energy efficiency of the heat sink, which can be attributed to the lowest pumping power. The liquid cooling experiments were then performed to verify that the maximum temperature of a SoW embedded with a parallel structure was decreased by more than 39% compared to that of the SoW with natural cooling. The embedded wafer-level microchannel architectures could afford feasible approaches for the thermal management of the upcoming SoW integration.