Design of PMBus Controller for Digital Power Management Chip

The present paper introduces a PMBus controller with an integrated APB bus interface, aiming to tackle the issues of portability and applicability encountered in the domain of digital power management chips. The controller's topology, centered around a state machine, facilitates PMBus communication functionality. Additionally, the integration of an APB bus interface extends the system's capabilities. The designed controller is firstly simulated by software, and secondly, the designed controller was implemented in the FPGA chip XC7A100T and communicated with an STM32F103 microcontroller serving as a host computer. By examining the communication results, the timing accuracy and functional integrity of the PMBus controller were verified.